(1) FIELD OF THE INVENTION
This invention relates to planarization of integrated circuit wafers using shallow trench isolation and more particularly to a method of planarization using Chemical Mechanical Polishing.
(2) DESCRIPTION OF THE RELATED ART
In sub 0.5 micron applications the use of shallow trench isolation, STI, between devices in an integrated circuit wafer is frequently used in place of the local oxidation of silicon, LOCOS, process. It is important to have a planar surface for subsequent process steps after the shallow trench isolation regions have been formed. Chemical Mechanical Polishing, CMP, is frequently used for planarization but this method has problems of dishing and residual oxide on the wafer surface. This Patent Application describes a method using a Spin On Glass layer in combination with Chemical Mechanical Polishing to achieve planarization of integrated circuit wafers using shallow trench isolation.
U.S. Pat. No. 5,312,512 to Allman discusses the global planarization of integrated circuit wafers using Spin On Glass and Chemical Mechanical Polishing but uses a different method than that described in this Patent Application.
U.S. Pat. No. 5,246,884 to Jaso describes a Chemical Mechanical Polishing process for shallow trench isolation devices wherein trench areas have a slower polishing rate than the higher areas. This method does not discuss Spin On Glass.
The methods of this invention are described in a paper by the inventor entitled "SOG Smoothing Technique For Planarization of Shallow Trench Isolation," by Lai-Juh Chen et al., 1996 Proceedings First International Chemical-Mechanical Polish (C.M.P.) For VLSI/ULSI Multilevel Interconnection Conference (CMP-MIC), Feb. 22-23, 1996, pages 307-314.